1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a full complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell.
2. Description of the Related Art
An SRAM semiconductor memory device has a lower power consumption and a higher operation speed than a dynamic random access memory (DRAM). Thus, the SRAM device is widely used for cache memory of computer and portable electronic devices.
A memory cell of the SRAM device is divided into two types of cells, that is, one is a high load resistor cell employing a high load resistor as a load device, and the other is a CMOS type cell employing a PMOS transistor as a load device.
The CMOS type cell is also divided into two types of cells, that is, one is a thin-film transistor (TFT) cell employing a thin-film transistor (TFT) as the load device, and the other is a full CMOS cell employing a bulk transistor as the load device.
FIG. 1 is an equivalent circuit diagram of a general CMOS SRAM cell. Referring to FIG. 1, the CMOS SRAM cell is formed of a pair of driver transistors TD1 and TD2, a pair of transfer transistors TA1 and TA2, and a pair of load transistors TL1 and TL2. Here, the pair of driver transistors TD1 and TD2, and the pair of transfer transistors TA1 and TA2 are NMOS transistors. The pair of load transistors TL1 and TL2 are PMOS transistors.
A first driver transistor TD1 and a first transfer transistor TA1 are connected in series with each other. A source area of the first driver transistor TD1 is connected to a ground line Vss, and a drain area of the first transfer transistor TA1 is connected to a first bit line BL. Similarly, a second driver transistor TD2 and a second transfer transistor TA2 are also connected in series with each other. Also, a source area of the second driver transistor TD2 is connected to the ground line Vss, and a drain area of the second transfer transistor TA2 is connected to a second bit line /BL. The first and second bit lines BL and /BL maintain opposite information.
A source area and a drain area of a first load transistor TL1 are connected to a power line Vcc and a drain area of the first driver transistor TD1, namely, a first node N1, respectively. Similarly, a source area and a drain area of a second load transistor TL2 are connected to the power line Vcc and a drain area of the second driver transistor TD2, namely, a second node N2, respectively. A gate electrode of the first driver transistor TD1 and a gate electrode of the first load transistor TL1 are connected to the second node N2, and a gate electrode of the second driver transistor TD2 and a gate electrode of the second load transistor TL2 are connected to the first node N1. Also, gate electrodes of the first and second transfer transistors TA1 and TA2 are connected to a word line WL.
The above-described CMOS cell shows a lower stand-by current and a higher noise margin than a load resistor cell. Thus, the CMOS cell is widely used for a high-performance SRAM device requiring a low power supply voltage.
The equivalent circuit of the CMOS SRAM cell shown in FIG. 1 can be implemented on a semiconductor substrate in many configurations. FIG. 2 is a layout diagram of a conventional SRAM cell for implementing the equivalent circuit of the CMOS SRAM cell shown in FIG. 1 on the semiconductor substrate, and is one of many layout diagrams of an SRAM cell disclosed in a paper published by M. Ishida et al. (M. Ishida et al., IEDM 98, pp. 201-204). Also, M. Ishida et al. discloses the same cell layout diagram as that of the invention disclosed in the U.S. Pat. No. 5,654,915.
Referring to FIG. 2, a n-well region 21 is formed in a predetermined area of the semiconductor substrate, and an U-shaped first active region 23a is arranged in a p-well region around the n-well region 21. A second active region 23b parallel to an x-axis is arranged in the n-well region 21. A word line 25w is arranged on the semiconductor substrate so as to intersect the first active region 23a. The word line 25w is arranged parallel to the X-axis and intersects two parts of the first active region 23a. A first common gate electrode 25a intersecting the first active region 23a and the second active region 23b is arranged parallel to a y-axis. Also, a second common gate electrode 25b intersecting the first and second active regions 23a and 23b is arranged parallel to the y-axis. As a result, a pair of transfer transistors TA1 and TA2 and a pair of driver transistors TD1 and TD2, in which the word line 25w, the first common gate electrode 25a and the second common gate electrode 25b function as the gate electrode, are formed in the first active region 23a. Similarly, a pair of load transistors TL1 and TL2, in which the first common gate electrode 25a and the second common gate electrode 25b function as the gate electrode, are formed in the second active region 23b. As a result, the first driver transistor TD1 and the first load transistor TL1 form a first inverter, and the second driver transistor TD2 and the second load transistor TL2 form a second inverter.
A first node contact 27a is arranged on a drain area of the second driver transistor TD2 (an active region shared by the second driver transistor TD2 and the second transfer transistor TA2), a drain area of the second load transistor TL2, and the first common gate electrode 25a to expos them. And, a second node contact 27b is arranged on a drain area of the first driver transistor TD1 (an active region shared by the first driver transistor TD1 and the first transfer transistor TA1), a drain area of the first load transistor TL1, and the second common gate electrode 25b to expose them. Also, a ground contact 28s is arranged on the first active region 23a (a common source area of the first and second driver transistors TD1 and TD2) between the first common gate electrode 25a and the second common gate electrode 25b to expose itself. And, a power contact 28c is arranged on the second active region 23b (a common source area of the first and second load transistors TL1 and TL2) between the first common gate electrode 25a and the second common gate electrode 25b to expose itself. Further, first and second bit line contacts 29a and 29b are arranged on the first active region 23a adjacent to the word line 25w to expose itself.
The conventional full CMOS SRAM cell shown in FIG. 2 may be very sensitive to misarrangement during a photo process. Also, it is easy for leakage current to be caused in a node contact of the SRAM cell of FIG. 2.
FIG. 3 is a plan view of patterns in which the layout view of FIG. 2 is projected on the semiconductor substrate. Referring to FIG. 3, corner portions of actual active regions 23axe2x80x2 and 23bxe2x80x2 formed after a photo process are transformed into a round shape. In particular, the first active region 23a of FIG. 2 has two curved regions C and Cxe2x80x2, which are curved by 90xc2x0. Thus, it is easy for crystalline defects to be caused in the semiconductor substrate around the curved regions C and Cxe2x80x2. This is the reason why stress or damage from etching is concentrically applied to the curved regions while active regions are formed. In other words, this is the reason why stress from a pad nitride layer or damage from etching a trench is concentrated on the curved regions C and Cxe2x80x2, and as a result, it is easy for crystalline defects to be caused in the semiconductor substrate when a device isolation layer defining the active regions is formed by a local oxidation of silicon (LOCOS) process or a trench process. As a result, if the first and second node contacts (27a and 27b of FIG. 2) are formed in the curved regions C and Cxe2x80x2 in the following process, a leakage current flowing through each of the node contacts increases.
On the other hand, actual first and second common gate electrodes 25axe2x80x2 and 25bxe2x80x2 and an actual word line 25wxe2x80x2 are formed on the semiconductor substrate, in which the actual active regions 23axe2x80x2 and 23bxe2x80x2 are formed, by using a photomask, in which the first and second common gate electrodes 25a and 25b and the word line 25w of FIG. 2 are drawn. Here, as shown by a dotted line, when the first and second common gate electrodes 25axe2x80x3 and 25bxe2x80x3 are misaligned along the x-axis, the first driver transistor TD1 and the second driver transistor TD2 have different channel widths. Also, the first load transistor TL1 and the second load transistor TL2 have different channel widths. As a result, since the SRAM cell shows asymmetrical characteristics, cell stability deteriorates.
As described above, according to the prior art, since a node contact is formed in the curved region of an active region, leakage current characteristics of the node contact deteriorate. Also, in a case where misarrangement occurs during a photo process for forming gate patterns, cell stability deteriorates. Furthermore, it is difficult to reduce the length of a bit line perpendicular to a word line in one cell. With regard to the operation speed of the SRAM cell, for example, access time is increased more by a delay time caused by resistance and parasitic capacitance of the bit line than by a delay time caused by resistance and parasitic capacitance of the word line. Accordingly, minimizing the length of the bit line in one cell is very efficient in reducing the access time of the SRAM.
To solve the above problems, it is an object of the present invention to provide a full CMOS SRAM cell having a straight-line active region, for which it is possible to minimize the length of a bit line.
It is another object of the present invention to provide a full CMOS SRAM cell capable of increasing cell stability and improving leakage current characteristics of a node contact.
In accordance with the invention, there is provided a full CMOS SRAM cell. The full CMOS SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed parallel to the first active region on the semiconductor substrate between the first active region and the second active region, and a fourth active region is formed parallel to the second active region on the semiconductor substrate between the third active region and the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, parallel to the word line, and a second common conductive electrode intersects the second active region and the fourth active region, parallel to the word line. In one embodiment, the first through fourth active regions are formed to be straight lines. A first transfer transistor having the word line as a gate electrode is formed in the first active region. A first driver transistor having the first common conductive electrode as a gate electrode is formed in the first active region. A first load transistor having the first common conductive electrode as a gate electrode is formed in the third active region. A second transfer transistor having the word line as a gate electrode is formed in the second active region. A second driver transistor having the second common conductive electrode as a gate electrode is formed in the second active region. A second load transistor having the second common conductive electrode as a gate electrode is formed in the fourth active region.
In one embodiment, the first and second active regions are formed on a first conductive type semiconductor substrate, for example, on a p-type semiconductor substrate, and the third and fourth active regions are formed on a second conductive type semiconductor substrate, for example, on a n-type semiconductor substrate. Also, the p-type semiconductor substrate may be a p-well region, and the n-type semiconductor substrate may be a n-well region. As a result, a first transfer transistor using the word line for a gate electrode and a first driver transistor using the first common conductive electrode for a gate electrode are formed in series in the first active region. Similarly, a second transfer transistor using the word line for a gate electrode and a second driver transistor using the second common conductive electrode for a gate electrode are formed in series in the second active region. In one embodiment, the first and second driver transistors and the first and second transfer transistors are NMOS transistors. Also, a first load transistor using the first common conductive electrode line for a gate electrode is formed in the third active region, and a second load transistor using the second common conductive electrode for a gate electrode is formed in series in the fourth active region. In one embodiment, the first and second load transistors are PMOS transistors.
A drain area of the first driver transistor is formed in the first active region between the word line and the first common conductive electrode, and a drain area of the first load transistor is formed in the second active region between the word line and the first common conductive electrode. The drain area of the first driver transistor is electrically connected to the drain area of the first load transistor through a first node pad. Also, a drain area of the second driver transistor is formed in the second active region between the word line and the second common conductive electrode, and a drain area of the second load transistor is formed in the fourth active region between the word line and the second common conductive electrode. The drain area of the second driver transistor is electrically connected to the drain area of the second load transistor through a second node pad. Furthermore, the first node pad is electrically connected to the second common conductive electrode through a second local interconnection, and the second node pad is electrically connected to the first common conductive electrode through a first local interconnection. As a result, the first and second driver transistors and the first and second load transistors constitute one latch circuit.
The full CMOS SRAM cell further includes a first ground line electrically connected to a source area of the first driver transistor, and a second ground line electrically connected to a source area of the second driver transistor. The first and second ground lines are parallel to each other and intersect the word line. A first ground line pad may be further interposed between the first ground line and the source area of the first driver transistor. Similarly, a second ground line pad may be further interposed between the second ground line and the source area of the second driver transistor.
Also, the full CMOS SRAM cell further includes a power line electrically connected to the source areas of the first and second load transistors. The power line is arranged between the first and second ground lines and intersects the word line. A power line pad may be further interposed between the power line and the source area of the first and second load transistors.
The full CMOS SRAM cell further includes first and second bit lines parallel to each other. The first and second bit lines intersect the word line and are electrically connected to the drain area of the first transfer transistor and the drain area of the second transfer transistor, respectively. A first bit line pad may be further interposed between the first bit line and the drain area of the first transfer transistor. Similarly, a second bit line pad may be further interposed between the second bit line and the drain area of the second transfer transistor.
According to the present invention, the first through fourth active regions are arranged parallel to one other and are formed to be straight lines. Thus, physical stress or damage from etching, etc., applied to the edges of each of the active regions while a device isolation process for forming each of the active regions on the semiconductor substrate is performed, can be minimized. As a result, junction leakage current of the first and second active regions electrically connected to the first node pad and junction leakage current of the second and fourth active regions electrically connected to the second node pad can be substantially reduced. Also, even when the first and second common conductive electrodes are misaligned in the first through fourth active regions, a quantity of variation in a channel width of the first and second driver transistors is reduced considerably more than in the prior art. Thus, cell stability can be improved. Furthermore, the SRAM cell having a bit line which is shorter than the length of a word line can be implemented by the present invention. Accordingly, a delay time of a signal caused by resistance and parasitic capacitance of the bit line can be reduced.